// Copyright (C) 1953-2021 NUDT
// Verilog module name - time_sensitive_end 
// Version: V3.2.2.20210820
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//		  top of TSNNic
//				 
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module time_sensitive_end(
       i_clk,
       i_rst_n,
       
       iv_hcp_mid        ,
       //i_local_cnt_rst   ,        
       i_tsn_or_tte      ,	
		 i_sync_step_mode  , 
       iv_local_counter,
       //p0
       i_gmii_rxclk_p0,
       i_gmii_rst_n_p0,        
       iv_gmii_rxd_p0  ,
       i_gmii_rx_dv_p0 ,
       i_gmii_rx_er_p0 ,        
       ov_gmii_txd_p0  ,
       o_gmii_tx_en_p0 ,
       o_gmii_tx_er_p0 , 

	   iv_data_host,
	   i_data_wr_host,

	   ov_data_host,
	   o_data_wr_host,	   
       //p1 					
       //i_gmii_rxclk_p1,
       //i_gmii_rst_n_p1,        
       //iv_gmii_rxd_p1  ,
       //i_gmii_rx_dv_p1 ,
       //i_gmii_rx_er_p1 ,        
       //ov_gmii_txd_p1  ,
       //o_gmii_tx_en_p1 ,
       //o_gmii_tx_er_p1 ,    
       //p2
       //i_gmii_rxclk_p2,
       //i_gmii_rst_n_p2,        
       //iv_gmii_rxd_p2  ,
       //i_gmii_rx_dv_p2 ,
       //i_gmii_rx_er_p2 ,        
       //ov_gmii_txd_p2  ,
       //o_gmii_tx_en_p2 ,
       //o_gmii_tx_er_p2 ,    
       //p3	
       //i_gmii_rxclk_p3,
       //i_gmii_rst_n_p3,        
       //iv_gmii_rxd_p3  ,
       //i_gmii_rx_dv_p3 ,
       //i_gmii_rx_er_p3 ,        
       //ov_gmii_txd_p3  ,
       //o_gmii_tx_en_p3 ,
       //o_gmii_tx_er_p3 ,    
       
       o_osm_req_rx_pulse_p0    ,
       o_osm_resp_rx_pulse_p0   ,
       o_osm_req_tx_pulse_p0    ,
       o_osm_resp_tx_pulse_p0   ,
       
       o_osm_req_rx_pulse_p1    ,
       o_osm_resp_rx_pulse_p1   ,
       o_osm_req_tx_pulse_p1    ,
       o_osm_resp_tx_pulse_p1   ,
       
       o_osm_req_rx_pulse_p2    ,
       o_osm_resp_rx_pulse_p2   ,
       o_osm_req_tx_pulse_p2    ,
       o_osm_resp_tx_pulse_p2   ,
       
       o_osm_req_rx_pulse_p3    ,
       o_osm_resp_rx_pulse_p3   ,
       o_osm_req_tx_pulse_p3    ,
       o_osm_resp_tx_pulse_p3   ,
       
       i_data_wr_hcp,
       iv_data_hcp,
       ov_data_hcp,
       o_data_wr_hcp,

       iv_command,
	   i_command_wr,        
       ov_command_ack,
       o_command_ack_wr,        

       ov_tse_ver             ,  
       i_cyclestart          ,    
       i_rc_rxenable          ,
       i_st_rxenable          ,

       iv_syn_clk             ,
       o_PTO0                 ,
       o_PTO1                 ,
       o_PTO2                 ,
       o_PTO3                 ,
       
       o_mirror_pkt_wr        ,
       ov_mirror_pkt            
);

//I/O
input                   i_clk  ;                   //125Mhz
input                   i_rst_n;

input       [11:0]      iv_hcp_mid     ;
input                   i_tsn_or_tte   ;  
//input                   i_local_cnt_rst;
input       [39:0]		iv_local_counter;

input                   i_sync_step_mode;

input                   i_data_wr_hcp  ;
input      [8:0]        iv_data_hcp;                        
output     [8:0]        ov_data_hcp ;
output                  o_data_wr_hcp;

/////////////////////p0////////////////////
// clk & rst
input                   i_gmii_rxclk_p0    ;
input                   i_gmii_rst_n_p0  ;  		
//input data from gmii
input        [7:0]      iv_gmii_rxd_p0   ;
input                   i_gmii_rx_dv_p0  ;
input                   i_gmii_rx_er_p0  ;
//output data to gmii
output       [7:0]      ov_gmii_txd_p0;
output                  o_gmii_tx_en_p0;
output                  o_gmii_tx_er_p0;

input       [8:0]       iv_data_host;
input                   i_data_wr_host;

output      [8:0]       ov_data_host;
output                  o_data_wr_host;
///////////////////////p1////////////////////
//// clk & rst
//input                   i_gmii_rxclk_p1    ;
//input                   i_gmii_rst_n_p1  ; 
////input data from gmii
//input        [7:0]      iv_gmii_rxd_p1   ;
//input                   i_gmii_rx_dv_p1  ;
//input                   i_gmii_rx_er_p1  ;
////output data to gmii
//output       [7:0]      ov_gmii_txd_p1;
//output                  o_gmii_tx_en_p1;
//output                  o_gmii_tx_er_p1;
///////////////////////p2////////////////////
//// clk & rst
//input                   i_gmii_rxclk_p2    ;
//input                   i_gmii_rst_n_p2  ;
////input data from gmii
//input        [7:0]      iv_gmii_rxd_p2   ;
//input                   i_gmii_rx_dv_p2  ;
//input                   i_gmii_rx_er_p2  ;
////output data to gmii
//output       [7:0]      ov_gmii_txd_p2;
//output                  o_gmii_tx_en_p2;
//output                  o_gmii_tx_er_p2;
///////////////////////p3////////////////////
//// clk & rst
//input                   i_gmii_rxclk_p3    ;
//input                   i_gmii_rst_n_p3  ;   
////input data from gmii
//input        [7:0]      iv_gmii_rxd_p3   ;
//input                   i_gmii_rx_dv_p3  ;
//input                   i_gmii_rx_er_p3  ;
////output data to gmii
//output       [7:0]      ov_gmii_txd_p3;
//output                  o_gmii_tx_en_p3;
//output                  o_gmii_tx_er_p3;

output                  o_osm_req_rx_pulse_p0    ;
output                  o_osm_resp_rx_pulse_p0   ;
output                  o_osm_req_tx_pulse_p0    ;
output                  o_osm_resp_tx_pulse_p0   ;

output                  o_osm_req_rx_pulse_p1    ;
output                  o_osm_resp_rx_pulse_p1   ;
output                  o_osm_req_tx_pulse_p1    ;
output                  o_osm_resp_tx_pulse_p1   ;

output                  o_osm_req_rx_pulse_p2    ;
output                  o_osm_resp_rx_pulse_p2   ;
output                  o_osm_req_tx_pulse_p2    ;
output                  o_osm_resp_tx_pulse_p2   ;

output                  o_osm_req_rx_pulse_p3    ;
output                  o_osm_resp_rx_pulse_p3   ;
output                  o_osm_req_tx_pulse_p3    ;
output                  o_osm_resp_tx_pulse_p3   ;

input                   i_rc_rxenable                 ;
input                   i_st_rxenable                 ;
//command
input	   [63:0]	    iv_command;
input	         	    i_command_wr;
output     [63:0]	    ov_command_ack;
output    	            o_command_ack_wr;
output     [31:0]       ov_tse_ver;

input                   i_cyclestart                    ;
input      [79:0]       iv_syn_clk                    ;
output                  o_mirror_pkt_wr        ;
output     [8:0]        ov_mirror_pkt          ;
output                  o_PTO0                 ;
output                  o_PTO1                 ;
output                  o_PTO2                 ;
output                  o_PTO3                 ;

wire                    w_hardware_initial_finish;
//*******************************
//              hrp
//*******************************
wire       [2:0]        wv_ipv_smp2hbi             ;
wire       [4:0]        wv_inject_dbufid_smp2hbi   ; 
wire       [8:0]        wv_data_smp2hbi            ;
wire                    w_data_wr_smp2hbi          ;

wire       [8:0]        wv_bufid_pcb2hrp;
wire                    w_bufid_wr_pcb2hrp;
wire                    w_bufid_ack_hrp2pcb;

wire       [133:0]      wv_pkt_data_hrp2pcb;
wire                    w_pkt_data_wr_hrp2pcb;
wire       [15:0]       wv_pkt_addr_hrp2pcb;//11->15
wire                    w_pkt_ack_pcb2hrp;

wire       [45:0]       wv_ts_descriptor_hrp2flt;
wire                    w_ts_descriptor_wr_hrp2flt;
wire                    w_ts_descriptor_ack_flt2hrp;

wire       [45:0]       wv_nts_descriptor_hrp2flt;
wire                    w_nts_descriptor_wr_hrp2flt;
wire                    w_nts_descriptor_ack_flt2hrp;

wire       [31:0]       wv_st_stream_state_fic2hbi;
wire                    w_st_inject_overflow_pulse_hbi2fic;
//tsntag & bufid output for ip frame 
wire       [47:0]       wv_ip_tsntag_hrp2scp;
wire       [2:0]        wv_pkt_type_hrp2scp;
wire       [8:0]        wv_ip_bufid_hrp2scp;
wire                    w_ip_descriptor_wr_hrp2scp;
wire                    w_ip_descriptor_ack_scp2hrp;
//*******************************
//              nip
//*******************************
//port0
wire       [8:0]        wv_bufid_pcb2nip_0;
wire                    w_bufid_wr_pcb2nip_0;
wire                    w_bufid_ack_hrp2nip_0;

wire                    w_descriptor_wr_hcptohost; 
wire                    w_inverse_map_lookup_flag_hcp2host;
wire                    w_descriptor_wr_hcptonetwork;
wire       [39:0]       wv_descriptor_hcp;
wire                    w_descriptor_ack_hosttohcp;
wire                    w_descriptor_ack_networktohcp;

wire                    w_descriptor_wr_p1tohost; 
wire                    w_descriptor_wr_p1tohcp;
wire       [39:0]       wv_descriptor_p1;
wire                    w_inverse_map_lookup_flag_p1tohost;
wire       [2:0]        wv_pkt_type_p1;
wire                    w_descriptor_ack_hosttop1;   
wire                    w_descriptor_ack_hcptop1;

wire       [133:0]      wv_pkt_data_pcb2nip_0;
wire                    w_pkt_data_wr_pcb2nip_0;
wire       [15:0]       wv_pkt_addr_pcb2nip_0;
wire                    w_pkt_ack_pcb2nip_0;

//port1
wire       [8:0]        wv_bufid_pcb2nip_1;
wire                    w_bufid_wr_pcb2nip_1;
wire                    w_bufid_ack_hrp2nip_1;

wire       [45:0]       wv_descriptor_pcb2nip_1;
wire                    w_descriptor_wr_pcb2nip_1;
wire                    w_descriptor_ack_pcb2nip_1;

wire       [133:0]      wv_pkt_data_pcb2nip_1;
wire                    w_pkt_data_wr_pcb2nip_1;
wire       [15:0]       wv_pkt_addr_pcb2nip_1;
wire                    w_pkt_ack_pcb2nip_1;
//*******************************
//              flt
//*******************************
wire       [8:0]        wv_pkt_bufid_flt2pcb;    
wire                    w_pkt_bufid_wr_flt2pcb;  
wire       [3:0]        wv_pkt_bufid_cnt_flt2pcb;
//port0
wire       [8:0]        wv_pkt_bufid_flt2nop_0;
wire       [2:0]        wv_pkt_type_flt2nop_0;
wire                    w_pkt_bufid_wr_flt2nop_0;

//port1
wire       [8:0]        wv_pkt_bufid_flt2nop_1;
wire       [2:0]        wv_pkt_type_flt2nop_1;
wire                    w_pkt_bufid_wr_flt2nop_1;

//port2
wire       [8:0]        wv_pkt_bufid_flt2nop_2;
wire       [2:0]        wv_pkt_type_flt2nop_2;
wire                    w_pkt_bufid_wr_flt2nop_2;

//port3
wire       [8:0]        wv_pkt_bufid_flt2nop_3;
wire       [2:0]        wv_pkt_type_flt2nop_3;
wire                    w_pkt_bufid_wr_flt2nop_3;

//host port
wire       [8:0]        wv_pkt_bufid_flt2nop;
wire       [2:0]        wv_pkt_type_flt2nop;
wire       [4:0]        wv_submit_addr_flt2nop;
wire       [3:0]        wv_inport_flt2nop;
wire                    w_pkt_bufid_wr_flt2nop;
//*******************************
//            htp
//*******************************
wire       [8:0]        wv_pkt_bufid_htp2pcb;    
wire                    w_pkt_bufid_wr_htp2pcb;  
wire                    w_pkt_bufid_ack_pcb2htp; 

wire       [15:0]       wv_pkt_raddr_htp2pcb;    //11->15  
wire                    w_pkt_rd_htp2pcb;       
wire                    w_pkt_raddr_ack_pcb2htp;

wire       [133:0]      wv_pkt_data_pcb2htp;  
wire                    w_pkt_data_wr_pcb2htp;

wire                    w_ctag_rtag_flag_hbo2srm ;
wire       [8:0]        wv_data_hbo2srm          ;
wire                    w_data_wr_hbo2srm        ;
wire                    w_data_ready_srm2hbo     ;
//*******************************
//             nop
//*******************************
//port0
wire       [8:0]        wv_pkt_bufid_nop2pcb_0;    
wire                    w_pkt_bufid_wr_nop2pcb_0;  
wire                    w_pkt_bufid_ack_pcb2nop_0; 

wire       [15:0]       wv_pkt_raddr_nop2pcb_0; //11->15  
wire                    w_pkt_rd_nop2pcb_0;       
wire                    w_pkt_raddr_ack_pcb2nop_0;

wire       [133:0]      wv_pkt_data_pcb2nop_0;  
wire                    w_pkt_data_wr_pcb2nop_0;

//port1
wire       [8:0]        wv_pkt_bufid_nop2pcb_1;    
wire                    w_pkt_bufid_wr_nop2pcb_1;  
wire                    w_pkt_bufid_ack_pcb2nop_1; 

wire       [15:0]       wv_pkt_raddr_nop2pcb_1;    //11->15  
wire                    w_pkt_rd_nop2pcb_1;       
wire                    w_pkt_raddr_ack_pcb2nop_1;

wire       [133:0]      wv_pkt_data_pcb2nop_1;  
wire                    w_pkt_data_wr_pcb2nop_1;

wire       [8:0]        wv_data_nbo2frp       ;   
wire                    w_data_wr_nbo2frp     ;
wire                    w_data_ready_frp2nbo  ;           

wire       [8:0]        wv_free_bufid_fifo_rdusedw;

wire      [8:0]        wv_be_threshold_value_grm2nip           ;
wire      [8:0]        wv_rc_threshold_value_grm2nip           ;
wire      [8:0]        wv_standardpkt_threshold_value_grm2nip  ;
//command to each module
wire      [18:0]       wv_addr_mih2other      ;
wire      [31:0]       wv_wdata_mih2other     ;

wire                    w_wr_ffi_p8_mih2ffi ;
wire                    w_rd_ffi_p8_mih2ffi ;
wire                    w_wr_dex_p8_mih2dex ;
wire                    w_rd_dex_p8_mih2dex ;
wire                    w_wr_ctx_p8_mih2ctx ;
wire                    w_rd_ctx_p8_mih2ctx ;

wire                    w_wr_ffi_p0_mih2ffi ;
wire                    w_rd_ffi_p0_mih2ffi ;
wire                    w_wr_dex_p0_mih2dex ;
wire                    w_rd_dex_p0_mih2dex ;
wire                    w_wr_ctx_p0_mih2ctx ;
wire                    w_rd_ctx_p0_mih2ctx ;

wire                    w_wr_ffi_p1_mih2ffi ;
wire                    w_rd_ffi_p1_mih2ffi ;
wire                    w_wr_dex_p1_mih2dex ;
wire                    w_rd_dex_p1_mih2dex ;
wire                    w_wr_ctx_p1_mih2ctx ;
wire                    w_rd_ctx_p1_mih2ctx ;

wire                    w_wr_ffi_p2_mih2ffi ;
wire                    w_rd_ffi_p2_mih2ffi ;
wire                    w_wr_dex_p2_mih2dex ;
wire                    w_rd_dex_p2_mih2dex ;
wire                    w_wr_ctx_p2_mih2ctx ;
wire                    w_rd_ctx_p2_mih2ctx ;

wire                    w_wr_ffi_p3_mih2ffi ;
wire                    w_rd_ffi_p3_mih2ffi ;
wire                    w_wr_frm_mih2dex ;
wire                    w_rd_frm_mih2dex ;
wire                    w_wr_tic_mih2ctx ;
wire                    w_rd_tic_mih2ctx ;

wire              w_wr_cit2pcb;
wire              w_rd_cit2pcb;

wire              w_wr_cit2qgc0;
wire              w_rd_cit2qgc0;

wire              w_wr_cit2qgc1;
wire              w_rd_cit2qgc1;

wire              w_wr_cit2qgc2;
wire              w_rd_cit2qgc2;

wire              w_wr_cit2fim;
wire              w_rd_cit2fim;  

wire              w_wr_mih2rfe     ;
wire              w_rd_mih2rfe     ;

wire              w_wr_mih2mac_p0  ;
wire              w_rd_mih2mac_p0  ;

wire              w_wr_mih2mac_p1  ;
wire              w_rd_mih2mac_p1  ;

wire              w_wr_mih2mac_p2  ;
wire              w_rd_mih2mac_p2  ;

wire              w_wr_mih2mac_p3  ;
wire              w_rd_mih2mac_p3  ;

wire              w_wr_mih2tau  ;
wire              w_rd_mih2tau  ;

wire              w_wr_ffi_p8_ffi2mih            ;             
wire   [18:0]     wv_addr_ffi_p8_ffi2mih         ;     
wire   [31:0]     wv_rdata_ffi_p8_ffi2mih        ;     
                                     
wire              w_wr_dex_p8_dex2mih            ;     
wire   [18:0]     wv_addr_dex_p8_dex2mih         ;     
wire   [31:0]     wv_rdata_dex_p8_dex2mih        ;     
                                    
wire              w_wr_ctx_p8_ctx2mih            ;     
wire   [18:0]     wv_addr_ctx_p8_ctx2mih         ;     
wire   [31:0]     wv_rdata_ctx_p8_ctx2mih        ;      
                                       
wire              w_wr_ffi_p0_ffi2mih            ;     
wire   [18:0]     wv_addr_ffi_p0_ffi2mih         ;     
wire   [31:0]     wv_rdata_ffi_p0_ffi2mih        ;     
                                        
wire              w_wr_dex_p0_dex2mih            ;     
wire   [18:0]     wv_addr_dex_p0_dex2mih         ;     
wire   [31:0]     wv_rdata_dex_p0_dex2mih        ;     
                                       
wire              w_wr_ctx_p0_ctx2mih            ;     
wire   [18:0]     wv_addr_ctx_p0_ctx2mih         ;     
wire   [31:0]     wv_rdata_ctx_p0_ctx2mih        ;     

wire              w_wr_ffi_p1_ffi2mih            ;     
wire   [18:0]     wv_addr_ffi_p1_ffi2mih         ;     
wire   [31:0]     wv_rdata_ffi_p1_ffi2mih        ;     
                                       
wire              w_wr_dex_p1_dex2mih            ;     
wire   [18:0]     wv_addr_dex_p1_dex2mih         ;     
wire   [31:0]     wv_rdata_dex_p1_dex2mih        ;     
                                       
wire              w_wr_ctx_p1_ctx2mih            ;     
wire   [18:0]     wv_addr_ctx_p1_ctx2mih         ;     
wire   [31:0]     wv_rdata_ctx_p1_ctx2mih        ;      
                                      
wire              w_wr_ffi_p2_ffi2mih            ;     
wire   [18:0]     wv_addr_ffi_p2_ffi2mih         ;     
wire   [31:0]     wv_rdata_ffi_p2_ffi2mih        ;     
                                    
wire              w_wr_dex_p2_dex2mih            ;     
wire   [18:0]     wv_addr_dex_p2_dex2mih         ;     
wire   [31:0]     wv_rdata_dex_p2_dex2mih        ;     
                                     
wire              w_wr_ctx_p2_ctx2mih            ;     
wire   [18:0]     wv_addr_ctx_p2_ctx2mih         ;     
wire   [31:0]     wv_rdata_ctx_p2_ctx2mih        ;       
                                    
wire              w_wr_ffi_p3_ffi2mih            ;     
wire   [18:0]     wv_addr_ffi_p3_ffi2mih         ;     
wire   [31:0]     wv_rdata_ffi_p3_ffi2mih        ;     
                                                                         
wire              w_wr_tic2mih            ;     
wire   [18:0]     wv_addr_tic2mih         ;     
wire   [31:0]     wv_rdata_tic2mih        ;       
                                
wire              w_wr_ctx_p7                    ;     
wire   [18:0]     wv_addr_ctx_p7                 ;     
wire   [31:0]     wv_rdata_ctx_p7                ; 
 
wire              w_wr_frm2mih        ;
wire   [18:0]     wv_addr_frm2mih     ;
wire   [31:0]     wv_rdata_frm2mih    ;
          
wire              w_wr_pcb2cit;
wire   [18:0]     wv_addr_pcb2cit;
wire   [31:0]     wv_rdata_pcb2cit;

wire              w_wr_qgc02cit;
wire   [18:0]     wv_addr_qgc02cit;
wire   [31:0]     wv_rdata_qgc02cit;

wire              w_wr_qgc12cit;
wire   [18:0]     wv_addr_qgc12cit;
wire   [31:0]     wv_rdata_qgc12cit;

wire              w_wr_qgc22cit;
wire   [18:0]     wv_addr_qgc22cit;
wire   [31:0]     wv_rdata_qgc22cit;

wire              w_wr_sim2cit;
wire   [18:0]     wv_addr_sim2cit;
wire   [31:0]     wv_rdata_sim2cit;

wire              w_wr_rfe2mih              ;   
wire   [18:0]     wv_addr_rfe2mih           ;
wire   [31:0]     wv_rdata_rfe2mih          ;

wire              w_wr_mac2mih_p0           ;
wire   [18:0]     wv_addr_mac2mih_p0        ;
wire   [31:0]     wv_rdata_mac2mih_p0       ;

wire              w_wr_mac2mih_p1           ;
wire   [18:0]     wv_addr_mac2mih_p1        ;
wire   [31:0]     wv_rdata_mac2mih_p1       ;

wire              w_wr_mac2mih_p2           ;
wire   [18:0]     wv_addr_mac2mih_p2        ;
wire   [31:0]     wv_rdata_mac2mih_p2       ;

wire              w_wr_mac2mih_p3           ;
wire   [18:0]     wv_addr_mac2mih_p3        ;
wire   [31:0]     wv_rdata_mac2mih_p3       ;

wire              w_wr_tau2mih              ;
wire   [18:0]     wv_addr_tau2mih           ;
wire   [31:0]     wv_rdata_tau2mih          ;
 
wire   [35:0]     wv_desp_nbi2fsc       ;          
wire              w_desp_wr_nbi2fsc     ;

wire              w_desp_wr_fsc2cbo     ;
wire   [11:0]     wv_desp_fsc2cbo       ;

wire              w_desp_wr_fsc2hos     ;             
wire   [11:0]     wv_desp_fsc2hos       ;

wire   [8:0]      wv_bufid_hos2hbo      ;
wire              w_bufid_wr_hos2hbo    ;
wire              w_bufid_ready_hbo2hos ;

wire              w_descriptor_wr_hcp2netework  ;
wire   [11:0]     wv_descriptor_hcp2netework    ;
wire              w_descriptor_ack_netework2hcp ;

wire   [16:0]     wv_desp_hbi2fic     ;
wire              w_desp_wr_hbi2fic   ;
//wire   [4:0]      wv_st_inject_dbufid_hbi2fic  ;

wire   [11:0]     wv_desp_fic2nos     ; 
wire              w_desp_wr_fic2nos   ;

wire   [11:0]     wv_desp_fic2hos     ;
wire              w_desp_wr_fic2hos   ;
wire              w_desp_ack_hos2fic  ;

wire   [8:0]      wv_pkt_bufid_nos2nbo     ;
wire              w_pkt_bufid_wr_nos2nbo   ;
wire              w_pkt_bufid_ack_nbo2nos  ;

wire              w_qbv_or_qch_grm2nop        ;
wire   [10:0]     wv_schedule_period_grm2other               ;
wire   [10:0]     wv_time_slot_length_grm2other              ;
wire              w_desp_wr_cbi2fic                          ;
wire   [35:0]     wv_desp_cbi2fic                            ;

wire   [8:0]      wv_data_rfe2nbi                            ;
wire              w_data_wr_rfe2nbi                          ;

wire                    w_data_wr_p0_frer2osm;
wire        [8:0]       wv_data_p0_frer2osm  ;
wire                    w_data_ready_p0_osm2frer;
wire                    w_data_wr_p0_osm2frer;
wire        [8:0]       wv_data_p0_osm2frer  ;

wire                    w_data_wr_p1_frer2osm;
wire        [8:0]       wv_data_p1_frer2osm  ;
wire                    w_data_ready_p1_osm2frer;
wire                    w_data_wr_p1_osm2frer;
wire        [8:0]       wv_data_p1_osm2frer  ;

wire                    w_data_wr_p2_frer2osm;
wire        [8:0]       wv_data_p2_frer2osm  ;
wire                    w_data_ready_p2_osm2frer;
wire                    w_data_wr_p2_osm2frer;
wire        [8:0]       wv_data_p2_osm2frer  ;

wire                    w_data_wr_p3_tse2osm;
wire        [8:0]       wv_data_p3_tse2osm  ;
wire                    w_data_ready_p3_osm2tse;
wire                    w_data_wr_p3_osm2tse;
wire        [8:0]       wv_data_p3_osm2tse  ;

wire                    w_data_wr_frer2tse    ;
wire        [8:0]       wv_data_frer2tse      ;
wire                    w_data_ready_frer2tse ;
wire                    w_data_wr_tse2frer    ;
wire        [8:0]       wv_data_tse2frer      ;   

wire                    w_osm_req_tx_pulse_p0_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p0_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p1_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p1_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p2_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p2_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p3_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p3_osm2hcp  ;

wire                    w_osm_req_rx_pulse_p0_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p0_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p1_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p1_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p2_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p2_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p3_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p3_osm2hcp  ;

media_access_control #(.osm_id(8'd0),.local_module_id(12'd1)) media_access_control_p0
(                    
.i_gmii_clk        (i_gmii_rxclk_p0              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p0            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_addr                  (wv_addr_mih2other       ),      
.iv_wdata                 (wv_wdata_mih2other      ),           
.i_wr                     (w_wr_mih2mac_p0       ),
.i_rd                     (w_rd_mih2mac_p0       ),                                                                     
.o_wr                     (w_wr_mac2mih_p0       ),
.ov_addr                  (wv_addr_mac2mih_p0    ),
.ov_rdata                 (wv_rdata_mac2mih_p0   ),				 

.iv_hcp_mid        (iv_hcp_mid                ),                                                    
//.i_local_cnt_rst   (i_local_cnt_rst           ), 
.iv_local_counter  (iv_local_counter),                
                                                                 
.i_port_type       (1'b0                       ),                
.i_tsn_or_tte      (i_tsn_or_tte               ),                
.i_sync_step_mode  (i_sync_step_mode           ),                  
                                                                 
.i_gmii_rx_dv      (i_gmii_rx_dv_p0            ),                
.i_gmii_rx_er      (i_gmii_rx_er_p0            ),
.iv_gmii_rxd       (iv_gmii_rxd_p0             ),
.o_gmii_tx_en      (o_gmii_tx_en_p0            ),
.o_gmii_tx_er      (o_gmii_tx_er_p0            ),
.ov_gmii_txd       (ov_gmii_txd_p0             ),
                                               
.i_data_wr         (w_data_wr_nbo2frp               ),     
.iv_data           (wv_data_nbo2frp                 ),     
.o_data_ready      (w_data_ready_frp2nbo            ),     
.o_data_wr         (w_data_wr_p0_osm2frer           ), 
.ov_data           (wv_data_p0_osm2frer             ),  
                                                            
.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p0 ),               
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p0),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p0 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p0)

);
/*
media_access_control #(.osm_id(8'd1),.local_module_id(12'd2))media_access_control_p1
(                    
.i_gmii_clk        (i_gmii_rxclk_p1              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p1            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_addr                  (wv_addr_mih2other       ),      
.iv_wdata                 (wv_wdata_mih2other      ),           
.i_wr                     (w_wr_mih2mac_p1       ),
.i_rd                     (w_rd_mih2mac_p1       ),                                                                     
.o_wr                     (w_wr_mac2mih_p1       ),
.ov_addr                  (wv_addr_mac2mih_p1    ),
.ov_rdata                 (wv_rdata_mac2mih_p1   ),	

.iv_hcp_mid        (iv_hcp_mid                ),                                                
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
.i_sync_step_mode  (i_sync_step_mode           ),   
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p1            ),
.i_gmii_rx_er      (i_gmii_rx_er_p1            ),
.iv_gmii_rxd       (iv_gmii_rxd_p1             ),
.o_gmii_tx_en      (o_gmii_tx_en_p1            ),
.o_gmii_tx_er      (o_gmii_tx_er_p1            ),
.ov_gmii_txd       (ov_gmii_txd_p1             ),
                                               
.i_data_wr         (w_data_wr_p1_frer2osm               ),
.iv_data           (wv_data_p1_frer2osm                 ),
.o_data_ready      (w_data_ready_p1_osm2frer            ),
.o_data_wr         (w_data_wr_p1_osm2frer               ),
.ov_data           (wv_data_p1_osm2frer                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p1 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p1),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p1 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p1)

);

media_access_control #(.osm_id(8'd2),.local_module_id(12'd3))media_access_control_p2
(                    
.i_gmii_clk        (i_gmii_rxclk_p2              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p2            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_addr                  (wv_addr_mih2other       ),      
.iv_wdata                 (wv_wdata_mih2other      ),           
.i_wr                     (w_wr_mih2mac_p2       ),
.i_rd                     (w_rd_mih2mac_p2       ),                                                                     
.o_wr                     (w_wr_mac2mih_p2       ),
.ov_addr                  (wv_addr_mac2mih_p2    ),
.ov_rdata                 (wv_rdata_mac2mih_p2   ),	

.iv_hcp_mid        (iv_hcp_mid                ),                                                
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
.i_sync_step_mode  (i_sync_step_mode           ),   
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p2            ),
.i_gmii_rx_er      (i_gmii_rx_er_p2            ),
.iv_gmii_rxd       (iv_gmii_rxd_p2             ),
.o_gmii_tx_en      (o_gmii_tx_en_p2            ),
.o_gmii_tx_er      (o_gmii_tx_er_p2            ),
.ov_gmii_txd       (ov_gmii_txd_p2             ),
                                               
.i_data_wr         (w_data_wr_p2_frer2osm               ),
.iv_data           (wv_data_p2_frer2osm                 ),
.o_data_ready      (w_data_ready_p2_osm2frer            ),
.o_data_wr         (w_data_wr_p2_osm2frer               ),
.ov_data           (wv_data_p2_osm2frer                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p2 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p2),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p2 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p2)

);

media_access_control #(.osm_id(8'd3),.local_module_id(12'd4))media_access_control_p3
(                    
.i_gmii_clk        (i_gmii_rxclk_p3              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p3            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_addr                  (wv_addr_mih2other       ),      
.iv_wdata                 (wv_wdata_mih2other      ),           
.i_wr                     (w_wr_mih2mac_p3       ),
.i_rd                     (w_rd_mih2mac_p3       ),                                                                     
.o_wr                     (w_wr_mac2mih_p3       ),
.ov_addr                  (wv_addr_mac2mih_p3    ),
.ov_rdata                 (wv_rdata_mac2mih_p3   ),	

.iv_hcp_mid        (iv_hcp_mid                ),                                                 
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
.i_sync_step_mode  (i_sync_step_mode           ),   
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p3            ),
.i_gmii_rx_er      (i_gmii_rx_er_p3            ),
.iv_gmii_rxd       (iv_gmii_rxd_p3             ),
.o_gmii_tx_en      (o_gmii_tx_en_p3            ),
.o_gmii_tx_er      (o_gmii_tx_er_p3            ),
.ov_gmii_txd       (ov_gmii_txd_p3             ),
                                               
.i_data_wr         (w_data_wr_p3_tse2osm               ),
.iv_data           (wv_data_p3_tse2osm                 ),
.o_data_ready      (w_data_ready_p3_osm2tse            ),
.o_data_wr         (w_data_wr_p3_osm2tse               ),
.ov_data           (wv_data_p3_osm2tse                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p3 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p3),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p3 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p3)

);
*/
//host input
stream_mapping stream_mapping_inst(
.i_clk                              (i_clk                      )  ,
.i_rst_n                            (i_rst_n                    )  ,
                                                                
.iv_addr                            (wv_addr_mih2other                    )  ,
.iv_wdata                           (wv_wdata_mih2other                   )  ,
.i_wr                               (w_wr_frm_mih2dex                   )  ,
.i_rd                               (w_rd_frm_mih2dex                   )  ,                                                             
.o_wr                               (w_wr_frm2mih                   )  ,
.ov_addr                            (wv_addr_frm2mih                )  ,
.ov_rdata                           (wv_rdata_frm2mih               )  ,
                                                                
.iv_data                            (iv_data_host  ),//(wv_data_p3_osm2tse                   ),//(wv_data_hrx2frm            )  ,
.i_data_wr                          (i_data_wr_host),//(w_data_wr_p3_osm2tse                 ),//(w_data_wr_hrx2frm          )  ,

.ov_ipv                             (wv_ipv_smp2hbi             ),                                                                                                                                          
.ov_inject_dbufid                   (wv_inject_dbufid_smp2hbi   )  ,                                                                                                             
.ov_data                            (wv_data_smp2hbi            )  ,                                      
.o_data_wr                          (w_data_wr_smp2hbi          )
);

host_buffer_input host_buffer_input_inst(
.i_clk                          (i_clk                  ),
.i_rst_n                        (i_rst_n                ),
                                                                    
.iv_addr                        (wv_addr_mih2other        ),
.iv_wdata                       (wv_wdata_mih2other       ),
.i_wr                           (w_wr_ffi_p3_mih2ffi    ),
.i_rd                           (w_rd_ffi_p3_mih2ffi    ),                                                                  
.o_wr                           (w_wr_ffi_p3_ffi2mih          ),                      
.ov_addr                        (wv_addr_ffi_p3_ffi2mih       ), 
.ov_rdata                       (wv_rdata_ffi_p3_ffi2mih      ), 
                                                                   
.i_data_wr                      (w_data_wr_smp2hbi          )  ,
.iv_data                        (wv_data_smp2hbi            )  ,
.iv_ipv                         (wv_ipv_smp2hbi             )  ,
.iv_inject_dbufid               (wv_inject_dbufid_smp2hbi   )  , 
       
.iv_pkt_bufid                   (wv_bufid_pcb2hrp             ),
.i_pkt_bufid_wr                 (w_bufid_wr_pcb2hrp           ),
.o_pkt_bufid_ack                (w_bufid_ack_hrp2pcb          ),
                                                             
.ov_pkt                         (wv_pkt_data_hrp2pcb          ),
.o_pkt_wr                       (w_pkt_data_wr_hrp2pcb        ),
.ov_pkt_bufadd                  (wv_pkt_addr_hrp2pcb          ),
.i_pkt_ack                      (w_pkt_ack_pcb2hrp            ),

.iv_st_stream_state             (wv_st_stream_state_fic2hbi   ),
.o_st_inject_overflow_pulse     (w_st_inject_overflow_pulse_hbi2fic   ),

.i_hardware_initial_finish      (w_hardware_initial_finish    ),
                                                                                                                        
.ov_desp                        (wv_desp_hbi2fic         ),
//.ov_st_inject_dbufid            (wv_st_inject_dbufid_hbi2fic),                                      
.o_desp_wr                      (w_desp_wr_hbi2fic    ),                                                    

.iv_free_bufid_num              (wv_free_bufid_fifo_rdusedw             ),
.iv_hpriority_be_threshold_value(wv_be_threshold_value_grm2nip          ),
.iv_rc_threshold_value          (wv_rc_threshold_value_grm2nip          ),
.iv_lpriority_be_threshold_value(wv_standardpkt_threshold_value_grm2nip ),
.i_rc_rxenable                  (i_rc_rxenable                      ),
.i_st_rxenable                  (i_st_rxenable                      )
);

frame_injection_control frame_injection_control_inst
(
.i_clk                            (i_clk                   ),
.i_rst_n                          (i_rst_n                 ),
                                                           
.iv_addr                          (wv_addr_mih2other                 ),      
.iv_wdata                         (wv_wdata_mih2other                ),           
.i_wr_sis                         (w_wr_tic_mih2ctx                ),
.i_rd_sis                         (w_rd_tic_mih2ctx                ), 
.i_wr_sim                         (w_wr_cit2fim                ),
.i_rd_sim                         (w_rd_cit2fim                ),         
                                                           
.o_wr_sis                         (w_wr_tic2mih                ),
.ov_addr_sis                      (wv_addr_tic2mih             ),
.ov_rdata_sis                     (wv_rdata_tic2mih            ),
.o_wr_sim                         (w_wr_sim2cit                ),
.ov_addr_sim                      (wv_addr_sim2cit             ),
.ov_rdata_sim                     (wv_rdata_sim2cit            ), 
                                                           
.i_st_rxenable                    (i_st_rxenable           ),
.i_cycle_start                    (i_cyclestart           ),
.iv_time_slot_length              (wv_time_slot_length_grm2other    ),
.iv_time_slot_period              (wv_schedule_period_grm2other     ),
                                                           
.i_desp_wr_hcp                    (w_desp_wr_cbi2fic                ), 
.iv_desp_hcp                      (wv_desp_cbi2fic                  ), 
                                                                       
.i_desp_wr_host                   (w_desp_wr_hbi2fic          ),
.iv_desp_host                     (wv_desp_hbi2fic            ),
//.iv_st_inject_dbufid_host         (wv_st_inject_dbufid_hbi2fic   ),      
                                                           
.ov_desp_network                  (wv_desp_fic2nos                 ),
.o_desp_wr_network                (w_desp_wr_fic2nos               ),

.ov_desp_host                     (wv_desp_fic2hos    ), 
.o_desp_wr_host                   (w_desp_wr_fic2hos  ),
.i_desp_ack_host                  (w_desp_ack_hos2fic ),
                                                           
.ov_st_stream_state               (wv_st_stream_state_fic2hbi      ),
.i_st_inject_overflow_pulse       (w_st_inject_overflow_pulse_hbi2fic)
);
//network input
/*
redundant_frame_elimination redundant_frame_elimination_inst
(
    .i_clk           (i_clk           ),
    .i_rst_n         (i_rst_n         ),
    
    .iv_addr         (wv_addr_mih2other   ),      
    .iv_wdata        (wv_wdata_mih2other  ),           
    .i_wr            (w_wr_mih2rfe      ),
    .i_rd            (w_rd_mih2rfe      ),                                                                     
    .o_wr            (w_wr_rfe2mih      ),
    .ov_addr         (wv_addr_rfe2mih   ),
    .ov_rdata        (wv_rdata_rfe2mih  ),
                                
    .iv_data_p0      (wv_data_p0_osm2frer      ),                     
    .i_data_wr_p0    (w_data_wr_p0_osm2frer    ),                     
                                                             
    .iv_data_p1      (wv_data_p1_osm2frer  ),                     
    .i_data_wr_p1    (w_data_wr_p1_osm2frer),                     
                                    
    .iv_data_p2      (wv_data_p2_osm2frer  ),
    .i_data_wr_p2    (w_data_wr_p2_osm2frer),
                                     
    .ov_data         (wv_data_rfe2nbi         ),
    .o_data_wr       (w_data_wr_rfe2nbi       )       
);
*/
  //#(parameter network_port_or_hcp_port = 1'b0)//1'b0:network port.   1'b1:hcp port.    
network_buffer_input #(.inport(6'd0),.forward_mode(1'b0)) network_buffer_input_inst//forward_mode:0,cutthrough; 1,stored  
(
.i_clk                              (i_clk                     ),
.i_rst_n                            (i_rst_n                   ),          

.i_data_wr                          (w_data_wr_p0_osm2frer    ),  //(w_data_wr_rfe2nbi              ),
.iv_data                            (wv_data_p0_osm2frer      ),//(wv_data_rfe2nbi            ),

.iv_addr                            (wv_addr_mih2other           ),
.iv_wdata                           (wv_wdata_mih2other          ),                               
       
.i_wr_psc                           (w_wr_ffi_p1_mih2ffi         ),
.i_rd_psc                           (w_rd_ffi_p1_mih2ffi         ),                               
.i_wr_pdg                           (w_wr_dex_p1_mih2dex         ),
.i_rd_pdg                           (w_rd_dex_p1_mih2dex         ),
.o_wr_psc                           (w_wr_ffi_p1_ffi2mih         ),
.ov_addr_psc                        (wv_addr_ffi_p1_ffi2mih      ),
.ov_rdata_psc                       (wv_rdata_ffi_p1_ffi2mih     ),                                                                 
.o_wr_pdg                           (w_wr_dex_p1_dex2mih         ),
.ov_addr_pdg                        (wv_addr_dex_p1_dex2mih      ),
.ov_rdata_pdg                       (wv_rdata_dex_p1_dex2mih     ),
       
.i_hardware_initial_finish          (w_hardware_initial_finish          ),
.i_rc_rxenable                      (i_rc_rxenable                      ),
.i_st_rxenable                      (i_st_rxenable                      ),

.iv_pkt_bufid                       (wv_bufid_pcb2nip_1                 ),
.i_pkt_bufid_wr                     (w_bufid_wr_pcb2nip_1               ),                   
.o_pkt_bufid_ack                    (w_bufid_ack_hrp2nip_1              ),

.ov_desp                            (wv_desp_nbi2fsc          ),
.o_desp_wr                          (w_desp_wr_nbi2fsc        ), 

.ov_pkt                             (wv_pkt_data_pcb2nip_1              ),
.o_pkt_wr                           (w_pkt_data_wr_pcb2nip_1            ),
.ov_pkt_bufadd                      (wv_pkt_addr_pcb2nip_1              ),
.i_pkt_ack                          (w_pkt_ack_pcb2nip_1                ),

.iv_free_bufid_num                  (wv_free_bufid_fifo_rdusedw         ),
.iv_hpriority_be_threshold_value    (wv_be_threshold_value_grm2nip      ),
.iv_rc_threshold_value              (wv_rc_threshold_value_grm2nip      ),
.iv_lpriority_be_threshold_value    (wv_standardpkt_threshold_value_grm2nip )                                                                        
);
  //#(parameter network_port_or_hcp_port = 1'b0)//1'b0:network port.   1'b1:hcp port.  
hcp_buffer_input #(.inport(6'd32),.forward_mode(1'b1)) hcp_buffer_input_inst//forward_mode:0,cutthrough; 1,stored  
(
.i_clk                           (i_clk                     ),
.i_rst_n                         (i_rst_n                   ),          
              
.i_data_wr                       (i_data_wr_hcp             ),
.iv_data                         (iv_data_hcp           ),

.iv_addr                         (wv_addr_mih2other           ),
.iv_wdata                        (wv_wdata_mih2other          ),                               
.i_wr_psc                        (w_wr_ffi_p8_mih2ffi       ),
.i_rd_psc                        (w_rd_ffi_p8_mih2ffi       ),                               
.i_wr_pdg                        (w_wr_dex_p8_mih2dex       ),
.i_rd_pdg                        (w_rd_dex_p8_mih2dex       ),
.o_wr_psc                        (w_wr_ffi_p8_ffi2mih         ),
.ov_addr_psc                     (wv_addr_ffi_p8_ffi2mih      ),
.ov_rdata_psc                    (wv_rdata_ffi_p8_ffi2mih     ),                                                              
.o_wr_pdg                        (w_wr_dex_p8_dex2mih         ),
.ov_addr_pdg                     (wv_addr_dex_p8_dex2mih      ),
.ov_rdata_pdg                    (wv_rdata_dex_p8_dex2mih     ),	
       
.i_hardware_initial_finish       (w_hardware_initial_finish          ),
.i_rc_rxenable                   (i_rc_rxenable                      ),
.i_st_rxenable                   (i_st_rxenable                      ),

.iv_pkt_bufid                    (wv_bufid_pcb2nip_0                 ),            
.i_pkt_bufid_wr                  (w_bufid_wr_pcb2nip_0               ),
.o_pkt_bufid_ack                 (w_bufid_ack_hrp2nip_0              ),

.ov_desp                         (wv_desp_cbi2fic                    ), 
.o_desp_wr                       (w_desp_wr_cbi2fic                  ),   
//.ov_eth_type                     (                                   ),
//.ov_tsmp_subtype                 (),

.ov_pkt                          (wv_pkt_data_pcb2nip_0              ),
.o_pkt_wr                        (w_pkt_data_wr_pcb2nip_0            ),
.ov_pkt_bufadd                   (wv_pkt_addr_pcb2nip_0              ),
.i_pkt_ack                       (w_pkt_ack_pcb2nip_0                ),

.iv_free_bufid_num                 (wv_free_bufid_fifo_rdusedw             ),
.iv_hpriority_be_threshold_value   (wv_be_threshold_value_grm2nip          ),
.iv_rc_threshold_value             (wv_rc_threshold_value_grm2nip          ),
.iv_lpriority_be_threshold_value   (wv_standardpkt_threshold_value_grm2nip )
);

frame_submission_control  frame_submission_control_inst
(
        .i_clk            (i_clk          ),
        .i_rst_n          (i_rst_n        ),
         
        .iv_desp          (wv_desp_nbi2fsc        ),     
        .i_desp_wr        (w_desp_wr_nbi2fsc      ),
         
        .o_desp_wr_hcp    (w_desp_wr_fsc2cbo  ),
        .ov_desp_hcp      (wv_desp_fsc2cbo    ),
        
        .o_desp_wr_host   (w_desp_wr_fsc2hos ),
        .ov_desp_host     (wv_desp_fsc2hos   )
    );

reg       [8:0]        rv_pkt_bufid;    
reg                    r_pkt_bufid_wr;  
reg       [5:0]        rv_pkt_bufid_cnt;
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        rv_pkt_bufid <= 9'b0;
		r_pkt_bufid_wr <= 1'b0;
		rv_pkt_bufid_cnt <= 6'b0;
    end
    else begin
	    if(w_bufid_ack_hrp2nip_0 == 1'b1)begin
            rv_pkt_bufid <= wv_bufid_pcb2nip_0;
            r_pkt_bufid_wr <= 1'b1;
            rv_pkt_bufid_cnt <= 6'h1;
		end
        else if(w_bufid_ack_hrp2nip_1 == 1'b1)begin
            rv_pkt_bufid <= wv_bufid_pcb2nip_1;
            r_pkt_bufid_wr <= 1'b1;
            rv_pkt_bufid_cnt <= 6'h1;
        end
        else if(w_bufid_ack_hrp2pcb == 1'b1)begin
            rv_pkt_bufid <= wv_bufid_pcb2hrp;
            r_pkt_bufid_wr <= 1'b1;
            rv_pkt_bufid_cnt <= 6'h1;
        end 
        else begin
            rv_pkt_bufid <= 9'b0;
            r_pkt_bufid_wr <= 1'b0;
            rv_pkt_bufid_cnt <= 6'h0;
        end        
    end
end

shared_buffer_management shared_buffer_management_inst(
.i_clk                 (i_clk),
.i_rst_n                 (i_rst_n),

.iv_addr                 (wv_addr_mih2other     ),                                   
.iv_wdata                (wv_wdata_mih2other    ),                            
.i_wr                    (w_wr_cit2pcb        ),                        
.i_rd                    (w_rd_cit2pcb        ), 
.o_wr                    (w_wr_pcb2cit        ),                     
.ov_addr                 (wv_addr_pcb2cit     ),                  
.ov_rdata                (wv_rdata_pcb2cit    ),   
    
.iv_pkt_p0               (wv_pkt_data_pcb2nip_0),
.i_pkt_wr_p0             (w_pkt_data_wr_pcb2nip_0),
.iv_pkt_wr_bufadd_p0     (wv_pkt_addr_pcb2nip_0),
.o_pkt_wr_ack_p0         (w_pkt_ack_pcb2nip_0),
                         
.iv_pkt_p1               (wv_pkt_data_pcb2nip_1),
.i_pkt_wr_p1             (w_pkt_data_wr_pcb2nip_1),
.iv_pkt_wr_bufadd_p1     (wv_pkt_addr_pcb2nip_1),
.o_pkt_wr_ack_p1         (w_pkt_ack_pcb2nip_1),
                         
.iv_pkt_p2               (134'b0),//(wv_pkt_data_pcb2nip_2),
.i_pkt_wr_p2             (1'b0),//(w_pkt_data_wr_pcb2nip_2),
.iv_pkt_wr_bufadd_p2     (16'b0),//(wv_pkt_addr_pcb2nip_2),
.o_pkt_wr_ack_p2         (),//(w_pkt_ack_pcb2nip_2),

.iv_pkt_p3               (134'b0),//(wv_pkt_data_pcb2nip_3),
.i_pkt_wr_p3             (1'b0),//(w_pkt_data_wr_pcb2nip_3),
.iv_pkt_wr_bufadd_p3     (16'b0),//(wv_pkt_addr_pcb2nip_3),
.o_pkt_wr_ack_p3         (),//(w_pkt_ack_pcb2nip_3), 

.iv_pkt_p8               (wv_pkt_data_hrp2pcb),
.i_pkt_wr_p8             (w_pkt_data_wr_hrp2pcb),
.iv_pkt_wr_bufadd_p8     (wv_pkt_addr_hrp2pcb),  
.o_pkt_wr_ack_p8         (w_pkt_ack_pcb2hrp),

.iv_pkt_rd_bufadd_p0     (wv_pkt_raddr_nop2pcb_0),
.i_pkt_rd_p0             (w_pkt_rd_nop2pcb_0),
.o_pkt_rd_ack_p0         (w_pkt_raddr_ack_pcb2nop_0),
.ov_pkt_p0               (wv_pkt_data_pcb2nop_0),
.o_pkt_wr_p0             (w_pkt_data_wr_pcb2nop_0),
                         
.iv_pkt_rd_bufadd_p1     (wv_pkt_raddr_nop2pcb_1),
.i_pkt_rd_p1             (w_pkt_rd_nop2pcb_1),
.o_pkt_rd_ack_p1         (w_pkt_raddr_ack_pcb2nop_1),
.ov_pkt_p1               (wv_pkt_data_pcb2nop_1),   
.o_pkt_wr_p1             (w_pkt_data_wr_pcb2nop_1),

.iv_pkt_rd_bufadd_p2     (16'b0),//(wv_pkt_raddr_nop2pcb_2),
.i_pkt_rd_p2             (1'b0),//(w_pkt_rd_nop2pcb_2),
.o_pkt_rd_ack_p2         (),//(w_pkt_raddr_ack_pcb2nop_2),
.ov_pkt_p2               (),//(wv_pkt_data_pcb2nop_2),   
.o_pkt_wr_p2             (),//(w_pkt_data_wr_pcb2nop_2),

.iv_pkt_rd_bufadd_p3     (16'b0),//(wv_pkt_raddr_nop2pcb_3),
.i_pkt_rd_p3             (1'b0),//(w_pkt_rd_nop2pcb_3),
.o_pkt_rd_ack_p3         (),//(w_pkt_raddr_ack_pcb2nop_3),
.ov_pkt_p3               (),//(wv_pkt_data_pcb2nop_3),   
.o_pkt_wr_p3             (),//(w_pkt_data_wr_pcb2nop_3),

.iv_pkt_rd_bufadd_p8     (wv_pkt_raddr_htp2pcb),
.i_pkt_rd_p8             (w_pkt_rd_htp2pcb),
.o_pkt_rd_ack_p8         (w_pkt_raddr_ack_pcb2htp),
.ov_pkt_p8               (wv_pkt_data_pcb2htp), 
.o_pkt_wr_p8             (w_pkt_data_wr_pcb2htp),

.ov_pkt_bufid_p0         (wv_bufid_pcb2nip_0),
.o_pkt_bufid_wr_p0       (w_bufid_wr_pcb2nip_0),
.i_pkt_bufid_ack_p0      (w_bufid_ack_hrp2nip_0),
                         
.ov_pkt_bufid_p1         (wv_bufid_pcb2nip_1),
.o_pkt_bufid_wr_p1       (w_bufid_wr_pcb2nip_1),
.i_pkt_bufid_ack_p1      (w_bufid_ack_hrp2nip_1),
                         
.ov_pkt_bufid_p2         (),//(wv_bufid_pcb2nip_2),
.o_pkt_bufid_wr_p2       (),//(w_bufid_wr_pcb2nip_2),
.i_pkt_bufid_ack_p2      (1'b0),//(w_bufid_ack_hrp2nip_2),
                 
.ov_pkt_bufid_p3         (),//(wv_bufid_pcb2nip_3),
.o_pkt_bufid_wr_p3       (),//(w_bufid_wr_pcb2nip_3),
.i_pkt_bufid_ack_p3      (1'b0),//(w_bufid_ack_hrp2nip_3),

.ov_pkt_bufid_p8         (wv_bufid_pcb2hrp),
.o_pkt_bufid_wr_p8       (w_bufid_wr_pcb2hrp),
.i_pkt_bufid_ack_p8      (w_bufid_ack_hrp2pcb),

.i_pkt_bufid_wr_sfc      (r_pkt_bufid_wr),//(w_pkt_bufid_wr_flt2pcb),
.iv_pkt_bufid_sfc        (rv_pkt_bufid),//(wv_pkt_bufid_flt2pcb),
.iv_pkt_bufid_cnt_sfc    (rv_pkt_bufid_cnt),//(wv_pkt_bufid_cnt_flt2pcb),

.iv_pkt_bufid_p0         (wv_pkt_bufid_nop2pcb_0),
.i_pkt_bufid_wr_p0       (w_pkt_bufid_wr_nop2pcb_0),
.o_pkt_bufid_ack_p0      (w_pkt_bufid_ack_pcb2nop_0),

.iv_pkt_bufid_p1         (wv_pkt_bufid_nop2pcb_1),
.i_pkt_bufid_wr_p1       (w_pkt_bufid_wr_nop2pcb_1),
.o_pkt_bufid_ack_p1      (w_pkt_bufid_ack_pcb2nop_1),

.iv_pkt_bufid_p2         (9'b0),//(wv_pkt_bufid_nop2pcb_2),
.i_pkt_bufid_wr_p2       (1'b0),//(w_pkt_bufid_wr_nop2pcb_2),
.o_pkt_bufid_ack_p2      (),//(w_pkt_bufid_ack_pcb2nop_2),
             
.iv_pkt_bufid_p3         (9'b0),//(wv_pkt_bufid_nop2pcb_3),
.i_pkt_bufid_wr_p3       (1'b0),//(w_pkt_bufid_wr_nop2pcb_3),
.o_pkt_bufid_ack_p3      (),//(w_pkt_bufid_ack_pcb2nop_3),

.iv_pkt_bufid_p8         (wv_pkt_bufid_htp2pcb),
.i_pkt_bufid_wr_p8       (w_pkt_bufid_wr_htp2pcb),
.o_pkt_bufid_ack_p8      (w_pkt_bufid_ack_pcb2htp),

.ov_free_bufid_num(wv_free_bufid_fifo_rdusedw),
.o_hardware_initial_finish(w_hardware_initial_finish)
);
//host output
host_output_schedule host_output_schedule_inst(
.i_clk                          (i_clk    ),
.i_rst_n                        (i_rst_n  ),
        
.iv_desp_network                (wv_desp_fsc2hos     ),
.i_desp_wr_network              (w_desp_wr_fsc2hos   ),

.iv_desp_host                   (wv_desp_fic2hos    ), 
.i_desp_wr_host                 (w_desp_wr_fic2hos  ),
.o_desp_ack_host                (w_desp_ack_hos2fic ),

.ov_bufid                       (wv_bufid_hos2hbo     ),
.o_bufid_wr                     (w_bufid_wr_hos2hbo   ),
.i_bufid_ready                  (w_bufid_ready_hbo2hos)
);

shared_buffer_output #(.frame_gap(5'd2)) host_buffer_output_inst(
.i_clk                    (i_clk                ),
.i_rst_n                  (i_rst_n              ),

.iv_pkt_bufid             (wv_bufid_hos2hbo     ),
.i_pkt_bufid_wr           (w_bufid_wr_hos2hbo   ),
.o_pkt_bufid_ack          (w_bufid_ready_hbo2hos),

.ov_pkt_bufid             (wv_pkt_bufid_htp2pcb),
.o_pkt_bufid_wr           (w_pkt_bufid_wr_htp2pcb),
.i_pkt_bufid_ack          (w_pkt_bufid_ack_pcb2htp),  
                          
.ov_pkt_raddr             (wv_pkt_raddr_htp2pcb),
.o_pkt_rd                 (w_pkt_rd_htp2pcb),
.i_pkt_raddr_ack          (w_pkt_raddr_ack_pcb2htp),
                          
.iv_pkt_data              (wv_pkt_data_pcb2htp),
.i_pkt_data_wr            (w_pkt_data_wr_pcb2htp),

.ov_prc_state             ( ),
.ov_opc_state             ( ),

.ov_data                (wv_data_hbo2srm             ),
.o_data_wr              (w_data_wr_hbo2srm           ),
.i_data_ready           (w_data_ready_srm2hbo        )
);

stream_remapping stream_remapping_inst
(
.i_clk      (i_clk  ),
.i_rst_n    (i_rst_n),                

.iv_data           (wv_data_hbo2srm          ),
.i_data_wr         (w_data_wr_hbo2srm        ),
.o_data_ready      (w_data_ready_srm2hbo     ),

.ov_data                (ov_data_host  ),//(wv_data_p3_tse2osm  ),                       
.o_data_wr              (o_data_wr_host),//(w_data_wr_p3_tse2osm),                         
.i_data_ready           (1'b1          ) //(w_data_ready_p3_osm2tse)                  
);
//network output
network_output_schedule network_output_schedule_inst
(
        .i_clk                (i_clk              ),
        .i_rst_n              (i_rst_n            ),
                                                 
        .i_cycle_start        (i_cyclestart      ),
                                                  
        .iv_addr              (wv_addr_mih2other            ),  
        .iv_wdata             (wv_wdata_mih2other           ),                    
        .i_wr                 (w_wr_cit2qgc0               ),
        .i_rd                 (w_rd_cit2qgc0               ),
        .o_wr                 (w_wr_qgc02cit               ),
        .ov_addr              (wv_addr_qgc02cit            ),
        .ov_rdata             (wv_rdata_qgc02cit           ),
                                               
        .i_qbv_or_qch         (w_qbv_or_qch_grm2nop       ),
        .iv_time_slot_length  (wv_time_slot_length_grm2other),
        .iv_schedule_period   (wv_schedule_period_grm2other ),
        
        .iv_desp              (wv_desp_fic2nos ),
        .i_desp_wr            (w_desp_wr_fic2nos),
        
        //.iv_pkt_bufid         (wv_desp_fic2nos[8:0]       ),       
        //.iv_ipv               (wv_desp_fic2nos[11:9]             ),     
        //.i_pkt_bufid_wr       (w_desp_wr_fic2nos     ),     
                                             
        .ov_pkt_bufid         (wv_pkt_bufid_nos2nbo       ),
        .o_pkt_bufid_wr       (w_pkt_bufid_wr_nos2nbo     ),
        .i_pkt_bufid_ready      (w_pkt_bufid_ack_nbo2nos    )     
);

shared_buffer_output #(.frame_gap(5'd2)) network_buffer_output_inst(
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),

.iv_pkt_bufid           (wv_pkt_bufid_nos2nbo),
.i_pkt_bufid_wr         (w_pkt_bufid_wr_nos2nbo),
.o_pkt_bufid_ack        (w_pkt_bufid_ack_nbo2nos),

.ov_pkt_bufid           (wv_pkt_bufid_nop2pcb_1),
.o_pkt_bufid_wr         (w_pkt_bufid_wr_nop2pcb_1),
.i_pkt_bufid_ack        (w_pkt_bufid_ack_pcb2nop_1),  

.ov_pkt_raddr           (wv_pkt_raddr_nop2pcb_1),
.o_pkt_rd               (w_pkt_rd_nop2pcb_1),
.i_pkt_raddr_ack        (w_pkt_raddr_ack_pcb2nop_1),

.iv_pkt_data            (wv_pkt_data_pcb2nop_1),
.i_pkt_data_wr          (w_pkt_data_wr_pcb2nop_1),

.ov_data                (wv_data_nbo2frp     ),
.o_data_wr              (w_data_wr_nbo2frp   ),
.i_data_ready           (w_data_ready_frp2nbo),

.ov_prc_state           (),
.ov_opc_state           ()
);
/*
frame_replication frame_replication_inst
    (
        .i_clk            (i_clk),
        .i_rst_n          (i_rst_n),
                         
        .iv_data          (wv_data_nbo2frp),
        .i_data_wr        (w_data_wr_nbo2frp), 
        .o_data_ready     (w_data_ready_frp2nbo),        
                     
        .ov_data_p0       (wv_data_p0_frer2osm     ),  
        .o_data_wr_p0     (w_data_wr_p0_frer2osm   ),  
        .i_data_ready_p0  (w_data_ready_p0_osm2frer),        
                        
        .ov_data_p1       (wv_data_p1_frer2osm     ),
        .o_data_wr_p1     (w_data_wr_p1_frer2osm   ),   
        .i_data_ready_p1  (w_data_ready_p1_osm2frer),
                         
        .ov_data_p2       (wv_data_p2_frer2osm     ),
        .o_data_wr_p2     (w_data_wr_p2_frer2osm   ),
        .i_data_ready_p2  (w_data_ready_p2_osm2frer)      
    );
*/
//control output
hcp_buffer_output hcp_buffer_output_inst
(
        .i_clk                        (i_clk  ),
        .i_rst_n                      (i_rst_n),
                      
        .iv_desp                      (wv_desp_fsc2cbo     ),
        .i_desp_wr                    (w_desp_wr_fsc2cbo   ),
                       
        .ov_pkt_bufid                 (wv_pkt_bufid_nop2pcb_0   ),
        .o_pkt_bufid_wr               (w_pkt_bufid_wr_nop2pcb_0 ),
        .i_pkt_bufid_ack              (w_pkt_bufid_ack_pcb2nop_0), 
                        
        .ov_pkt_raddr                 (wv_pkt_raddr_nop2pcb_0   ),
        .o_pkt_rd                     (w_pkt_rd_nop2pcb_0       ),
        .i_pkt_raddr_ack              (w_pkt_raddr_ack_pcb2nop_0),
                       
        .iv_pkt_data                  (wv_pkt_data_pcb2nop_0  ),
        .i_pkt_data_wr                (w_pkt_data_wr_pcb2nop_0),
                      
        .o_pkt_output_pulse           (),
        .o_host_inqueue_discard_pulse (),     
        .o_fifo_overflow_pulse        (),       
                           
        .ov_data                   (ov_data_hcp ),
        .o_data_wr                 (o_data_wr_hcp)
);
management_interface_hub management_interface_hub_inst(
.i_clk		                      (i_clk                               ),
.i_rst_n	                      (i_rst_n                             ),
                                                                       
.iv_command                       (iv_command                          ), 
.i_command_wr                     (i_command_wr                        ),          
                                                                       
.ov_addr                          (wv_addr_mih2other                   ),
.ov_wdata                         (wv_wdata_mih2other                  ),

.o_wr_ffi_p8                      (w_wr_ffi_p8_mih2ffi),
.o_rd_ffi_p8                      (w_rd_ffi_p8_mih2ffi),
.o_wr_dex_p8                      (w_wr_dex_p8_mih2dex),
.o_rd_dex_p8                      (w_rd_dex_p8_mih2dex),
.o_wr_ctx_p8                      (w_wr_ctx_p8_mih2ctx),
.o_rd_ctx_p8                      (w_rd_ctx_p8_mih2ctx),

.o_wr_ffi_p0                      (w_wr_ffi_p0_mih2ffi),
.o_rd_ffi_p0                      (w_rd_ffi_p0_mih2ffi),
.o_wr_dex_p0                      (w_wr_dex_p0_mih2dex),
.o_rd_dex_p0                      (w_rd_dex_p0_mih2dex),
.o_wr_ctx_p0                      (w_wr_ctx_p0_mih2ctx),
.o_rd_ctx_p0                      (w_rd_ctx_p0_mih2ctx),

.o_wr_ffi_p1                      (w_wr_ffi_p1_mih2ffi),
.o_rd_ffi_p1                      (w_rd_ffi_p1_mih2ffi),
.o_wr_dex_p1                      (w_wr_dex_p1_mih2dex),
.o_rd_dex_p1                      (w_rd_dex_p1_mih2dex),
.o_wr_ctx_p1                      (w_wr_ctx_p1_mih2ctx),
.o_rd_ctx_p1                      (w_rd_ctx_p1_mih2ctx),

.o_wr_ffi_p2                      (w_wr_ffi_p2_mih2ffi),
.o_rd_ffi_p2                      (w_rd_ffi_p2_mih2ffi),
.o_wr_dex_p2                      (w_wr_dex_p2_mih2dex),
.o_rd_dex_p2                      (w_rd_dex_p2_mih2dex),
.o_wr_ctx_p2                      (w_wr_ctx_p2_mih2ctx),
.o_rd_ctx_p2                      (w_rd_ctx_p2_mih2ctx),

.o_wr_ffi_p3                      (w_wr_ffi_p3_mih2ffi),
.o_rd_ffi_p3                      (w_rd_ffi_p3_mih2ffi),
.o_wr_frm                         (w_wr_frm_mih2dex   ),
.o_rd_frm                         (w_rd_frm_mih2dex   ),
.o_wr_tic                         (w_wr_tic_mih2ctx   ),
.o_rd_tic                         (w_rd_tic_mih2ctx   ),	
                                                                                                                                          
.o_wr_pcb                         (w_wr_cit2pcb       ),
.o_rd_pcb                         (w_rd_cit2pcb       ),

.o_wr_frl                         (                   ),
.o_rd_frl                         (                   ),
                                                                       
.o_wr_qgc0                        (w_wr_cit2qgc0      ),
.o_rd_qgc0                        (w_rd_cit2qgc0      ),
                                                      
.o_wr_qgc1                        (w_wr_cit2qgc1      ),
.o_rd_qgc1                        (w_rd_cit2qgc1      ),
                                                      
.o_wr_qgc2                        (w_wr_cit2qgc2      ),
.o_rd_qgc2                        (w_rd_cit2qgc2      ),
                                                                       
.o_wr_sim                         (w_wr_cit2fim                       ),
.o_rd_sim                         (w_rd_cit2fim                       ),

.o_wr_rfe                         (w_wr_mih2rfe   ),
.o_rd_rfe                         (w_rd_mih2rfe   ),  
                                   
.o_wr_mac_p0                      (w_wr_mih2mac_p0),
.o_rd_mac_p0                      (w_rd_mih2mac_p0),  
                                   
.o_wr_mac_p1                      (w_wr_mih2mac_p1),
.o_rd_mac_p1                      (w_rd_mih2mac_p1),  
                                   
.o_wr_mac_p2                      (w_wr_mih2mac_p2),
.o_rd_mac_p2                      (w_rd_mih2mac_p2),  
                                   
.o_wr_mac_p3                      (w_wr_mih2mac_p3),
.o_rd_mac_p3                      (w_rd_mih2mac_p3), 

.o_wr_tau                         (w_wr_mih2tau),
.o_rd_tau                         (w_rd_mih2tau), 
                                  
.i_wr_ffi_p8                      (w_wr_ffi_p8_ffi2mih                 ),
.iv_addr_ffi_p8                   (wv_addr_ffi_p8_ffi2mih              ),
.iv_rdata_ffi_p8                  (wv_rdata_ffi_p8_ffi2mih             ),
                                                                       
.i_wr_dex_p8                      (w_wr_dex_p8_dex2mih                 ),
.iv_addr_dex_p8                   (wv_addr_dex_p8_dex2mih              ),
.iv_rdata_dex_p8                  (wv_rdata_dex_p8_dex2mih             ),
                                                                       
.i_wr_ctx_p8                      (w_wr_ctx_p8_ctx2mih                 ),
.iv_addr_ctx_p8                   (wv_addr_ctx_p8_ctx2mih              ),
.iv_rdata_ctx_p8                  (wv_rdata_ctx_p8_ctx2mih             ),
                                                                       
.i_wr_ffi_p0                      (w_wr_ffi_p0_ffi2mih                 ),
.iv_addr_ffi_p0                   (wv_addr_ffi_p0_ffi2mih              ),
.iv_rdata_ffi_p0                  (wv_rdata_ffi_p0_ffi2mih             ),
                                                                       
.i_wr_dex_p0                      (w_wr_dex_p0_dex2mih                 ),
.iv_addr_dex_p0                   (wv_addr_dex_p0_dex2mih              ),
.iv_rdata_dex_p0                  (wv_rdata_dex_p0_dex2mih             ),
                                                                       
.i_wr_ctx_p0                      (w_wr_ctx_p0_ctx2mih                 ),
.iv_addr_ctx_p0                   (wv_addr_ctx_p0_ctx2mih              ),
.iv_rdata_ctx_p0                  (wv_rdata_ctx_p0_ctx2mih             ),
                                                                       
.i_wr_ffi_p1                      (w_wr_ffi_p1_ffi2mih                 ),
.iv_addr_ffi_p1                   (wv_addr_ffi_p1_ffi2mih              ),
.iv_rdata_ffi_p1                  (wv_rdata_ffi_p1_ffi2mih             ),
                                                                       
.i_wr_dex_p1                      (w_wr_dex_p1_dex2mih                 ),
.iv_addr_dex_p1                   (wv_addr_dex_p1_dex2mih              ),
.iv_rdata_dex_p1                  (wv_rdata_dex_p1_dex2mih             ),
                                                                       
.i_wr_ctx_p1                      (w_wr_ctx_p1_ctx2mih                 ),
.iv_addr_ctx_p1                   (wv_addr_ctx_p1_ctx2mih              ),
.iv_rdata_ctx_p1                  (wv_rdata_ctx_p1_ctx2mih             ),
                                                                       
.i_wr_ffi_p2                      (w_wr_ffi_p2_ffi2mih                 ),
.iv_addr_ffi_p2                   (wv_addr_ffi_p2_ffi2mih              ),
.iv_rdata_ffi_p2                  (wv_rdata_ffi_p2_ffi2mih             ),
                                                                       
.i_wr_dex_p2                      (w_wr_dex_p2_dex2mih                 ),
.iv_addr_dex_p2                   (wv_addr_dex_p2_dex2mih              ),
.iv_rdata_dex_p2                  (wv_rdata_dex_p2_dex2mih             ),
                                                                       
.i_wr_ctx_p2                      (w_wr_ctx_p2_ctx2mih                 ),
.iv_addr_ctx_p2                   (wv_addr_ctx_p2_ctx2mih              ),
.iv_rdata_ctx_p2                  (wv_rdata_ctx_p2_ctx2mih             ),
                                                                       
.i_wr_ffi_p3                      (w_wr_ffi_p3_ffi2mih                 ),
.iv_addr_ffi_p3                   (wv_addr_ffi_p3_ffi2mih              ),
.iv_rdata_ffi_p3                  (wv_rdata_ffi_p3_ffi2mih             ),
                                                                       
.i_wr_frm                         (w_wr_frm2mih                        ),
.iv_addr_frm                      (wv_addr_frm2mih                     ),
.iv_rdata_frm                     (wv_rdata_frm2mih                    ),
                                                                              
.i_wr_tic                         (w_wr_tic2mih                        ),
.iv_addr_tic                      (wv_addr_tic2mih                     ),
.iv_rdata_tic                     (wv_rdata_tic2mih                    ),
                                 
.i_wr_pcb                         (w_wr_pcb2cit                        ),
.iv_addr_pcb                      (wv_addr_pcb2cit                     ),
.iv_rdata_pcb                     (wv_rdata_pcb2cit                    ),	

.i_wr_frl                         (1'b0 ), 
.iv_addr_frl                      (19'b0),
.iv_rdata_frl                     (32'b0),
                                                                                                                                             
.i_wr_qgc0                        (w_wr_qgc02cit                       ),
.iv_addr_qgc0                     (wv_addr_qgc02cit                    ),
.iv_rdata_qgc0                    (wv_rdata_qgc02cit                   ),
                                 
.i_wr_qgc1                        (w_wr_qgc12cit                       ),
.iv_addr_qgc1                     (wv_addr_qgc12cit                    ),
.iv_rdata_qgc1                    (wv_rdata_qgc12cit                   ),
                                                                      
.i_wr_qgc2                        (w_wr_qgc22cit                       ),
.iv_addr_qgc2                     (wv_addr_qgc22cit                    ),
.iv_rdata_qgc2                    (wv_rdata_qgc22cit                   ),
                                                                      
.i_wr_sim                         (w_wr_sim2cit                       ),
.iv_addr_sim                      (wv_addr_sim2cit                    ),
.iv_rdata_sim                     (wv_rdata_sim2cit                   ),

.i_wr_rfe                         (w_wr_rfe2mih                ),
.iv_addr_rfe                      (wv_addr_rfe2mih             ),
.iv_rdata_rfe                     (wv_rdata_rfe2mih            ),
                                  
.i_wr_mac_p0                      (w_wr_mac2mih_p0                ),
.iv_addr_mac_p0                   (wv_addr_mac2mih_p0             ),
.iv_rdata_mac_p0                  (wv_rdata_mac2mih_p0            ),
                                  
.i_wr_mac_p1                      (w_wr_mac2mih_p1                ),
.iv_addr_mac_p1                   (wv_addr_mac2mih_p1             ),
.iv_rdata_mac_p1                  (wv_rdata_mac2mih_p1            ),
                                  
.i_wr_mac_p2                      (w_wr_mac2mih_p2                ),
.iv_addr_mac_p2                   (wv_addr_mac2mih_p2             ),
.iv_rdata_mac_p2                  (wv_rdata_mac2mih_p2            ),
                                  
.i_wr_mac_p3                      (w_wr_mac2mih_p3                ),
.iv_addr_mac_p3                   (wv_addr_mac2mih_p3             ),
.iv_rdata_mac_p3                  (wv_rdata_mac2mih_p3            ),

.i_wr_tau                      (w_wr_tau2mih               ),
.iv_addr_tau                   (wv_addr_tau2mih            ),
.iv_rdata_tau                  (wv_rdata_tau2mih           ),
                                                                                                      
.ov_command_ack                   (ov_command_ack                      ),
.o_command_ack_wr                 (o_command_ack_wr                    ),

.ov_tse_ver                       (ov_tse_ver                            ),
.ov_hpriority_be_police_threshold (wv_be_threshold_value_grm2nip         ), 
.ov_rc_threshold_value            (wv_rc_threshold_value_grm2nip         ),
.ov_lpriority_be_police_threshold (wv_standardpkt_threshold_value_grm2nip),
.o_qbv_or_qch                     (w_qbv_or_qch_grm2nop                  ),          
.ov_time_slot_length              (wv_time_slot_length_grm2other         ),          
.ov_schedule_period               (wv_schedule_period_grm2other          )  
         
);
/*
testaux testaux_inst(	
	.i_clk 					(i_clk),
	.i_rst_n 				(i_rst_n),

    .iv_addr                (wv_addr_mih2other    ),
    .iv_wdata               (wv_wdata_mih2other     ),
    .i_wr                   (w_wr_mih2tau         ),
    .i_rd                   (w_rd_mih2tau         ),                     
    .o_wr                   (w_wr_tau2mih         ),
    .ov_addr                (wv_addr_tau2mih      ),
    .ov_rdata               (wv_rdata_tau2mih     ), 
	//gmii interfaces from p0
	.i_gmii_rxclk_p0		(i_gmii_rxclk_p0),
	.i_gmii_dv_p0			(i_gmii_rx_dv_p0),
	.iv_gmii_rxd_p0			(iv_gmii_rxd_p0),
	.i_gmii_rx_er_p0		(i_gmii_rx_er_p0),	
	
	.i_gmii_txclk_p0		(i_gmii_rxclk_p0),        
	.i_gmii_en_p0			(o_gmii_tx_en_p0 ),       
	.iv_gmii_txd_p0			(ov_gmii_txd_p0  ),       
	.i_gmii_tx_er_p0		(o_gmii_tx_er_p0 ),       
	                                                
	//gmii interfaces from p1                       
	.i_gmii_rxclk_p1		(i_gmii_rxclk_p1),      
	.i_gmii_dv_p1			(i_gmii_rx_dv_p1),         
	.iv_gmii_rxd_p1			(iv_gmii_rxd_p1),       
	.i_gmii_rx_er_p1		(i_gmii_rx_er_p1),	    
	                                                
	.i_gmii_txclk_p1		(i_gmii_rxclk_p1),     
	.i_gmii_en_p1			(o_gmii_tx_en_p1 ),   
	.iv_gmii_txd_p1			(ov_gmii_txd_p1  ),      
	.i_gmii_tx_er_p1		(o_gmii_tx_er_p1 ),      
	                                                
	//gmii interfaces from p2                       
	.i_gmii_rxclk_p2		(i_gmii_rxclk_p2),      
	.i_gmii_dv_p2			(i_gmii_rx_dv_p2),         
	.iv_gmii_rxd_p2			(iv_gmii_rxd_p2),
	.i_gmii_rx_er_p2		(i_gmii_rx_er_p2),	
	
	.i_gmii_txclk_p2		(i_gmii_rxclk_p2),
	.i_gmii_en_p2			(o_gmii_tx_en_p2),
	.iv_gmii_txd_p2			(ov_gmii_txd_p2),
	.i_gmii_tx_er_p2		(o_gmii_tx_er_p2),
	
	//gmii interfaces from p3
	.i_gmii_rxclk_p3		(i_gmii_rxclk_p3),
	.i_gmii_dv_p3			(i_gmii_rx_dv_p3),
	.iv_gmii_rxd_p3			(iv_gmii_rxd_p3),
	.i_gmii_rx_er_p3		(i_gmii_rx_er_p3),	
	
	.i_gmii_txclk_p3		(i_gmii_rxclk_p3),
	.i_gmii_en_p3			(o_gmii_tx_en_p3),
	.iv_gmii_txd_p3			(ov_gmii_txd_p3),
	.i_gmii_tx_er_p3		(o_gmii_tx_er_p3),
	
	.i_cyclestart			(i_cyclestart),
	.iv_synclk				(iv_syn_clk   ),
	.iv_hcp_mac				({24'h662662,iv_hcp_mid,12'h0}),    
	.i_table_trigger0		(1'b0),
	.i_table_trigger1		(1'b0),
			
	.o_PTO0					(o_PTO0            ),
	.o_PTO1					(o_PTO1            ),
	.o_PTO2					(o_PTO2            ),
	.o_PTO3					(o_PTO3            ),
	
	.o_mirror_pkt_wr		(o_mirror_pkt_wr	),
	.ov_mirror_pkt		    (ov_mirror_pkt  	)	                         	
);
*/
endmodule
 
